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Title:
METHOD FOR DECIDING ARRANGEMENT OF INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPH07141415
Kind Code:
A
Abstract:

PURPOSE: To decide an optimum arrangement form by ending the execution of a mini-cut method and detecting a stable net to be a factor for falling into a local stable state from nets when the number of cuts of the nets obtained by the execution of the mini-cut method reaches the local stable state.

CONSTITUTION: The mini-cut method execution program 2 of an integrated circuit cell arrangement deciding device 1 executes the mini-cut method of bisection and quadrasection so as to decide the cell arrangement of an integrated circuit corresponding to the mini-cut method. A stable net elimination program 3 also receives the cell net information of a local optimum state obtained by the mini-cut method execution program 2, detects the stable net to be the factor for falling into the local optimum state from the received nets, then, eliminates the stable net and starts the mini-cut execution program 2 again.


Inventors:
SHIBUYA TOSHIYUKI
Application Number:
JP28468293A
Publication Date:
June 02, 1995
Filing Date:
November 15, 1993
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H01L21/822; G06F17/50; H01L27/04; (IPC1-7): G06F17/50; H01L21/822; H01L27/04
Attorney, Agent or Firm:
Mitsuyoshi Okada (1 person outside)