Title:
METHOD FOR DESIGNING LOGIC CIRCUIT
Document Type and Number:
Japanese Patent JP2788882
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To shorten the design period of a logic circuit consisting of plural logic blocks partially using a new logic block of new design.
SOLUTION: A function description block 14 which performs logically the same operation as that of the new logic block 23, generated and built in instead of the new logic block 23, and the functions of the logic circuit 11 is simulated. Reference data B for verifying the new logic block 23 are generated from a function simulation result to design the circuit of the new logic block 23 and the logical simulation result is judged through a step wherein the logical simulation of the new logic block 23 is performed by using the reference data B.
Inventors:
UENO HIROAKI
Application Number:
JP30533195A
Publication Date:
August 20, 1998
Filing Date:
November 24, 1995
Export Citation:
Assignee:
YAMAGATA NIPPON DENKI KK
International Classes:
G06F17/50; (IPC1-7): G06F17/50
Domestic Patent References:
| JP7121587A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)