To provide a method of analyzing an electronic component having numerous solder bumps and BGAs, that enables reduction in the design period of the electronic component to significantly contribute to reducing the cost of the electronic component, by reducing the time needed for analysis of numerical simulations for predicting the electrical characteristics of the component, from several days to several hours.
When the electronic component, having numerous solder bumps 1 and BGAs, is analyzed in order to reduce the cost of the component, the component is replaced by a three-dimensional model where curves and curved surfaces, constituting the three-dimensional models of the solder bumps 1 and the BGAs, are approximated by polygons. The analysis is conducted using a finite-element model that uses a solid model created through the transformation of the three-dimensional model.
Tomoyasu Sakaguchi
Hiroki Naito
Next Patent: FUNCTION CALLING DEVICE AND PROGRAM FOR PROCESS OF CALLING FUNCTION