To suppress the cost of hardware by exactly controlling a frame transmission interval with a little arithmetic processing while maintaining a frame transfer rate higher than that of a transmission line.

When the internal processing speed of a packet transfer device is higher than the input speed of packets to a packet transfer device PT, the count operation of an internal cock synchronous counter (counter (1)) 200 synchronized to a clock to be used inside the packet transfer device and a transmission line cock synchronous counter (counter (2)) 201 synchronized to a clock on the transmission line is started simultaneously with the transmission start of frames. When the transmission of frames is completed, only the count operation of the internal clock synchronous counter is stopped. Until the counter value of the transmission line synchronous counter becomes equal with the counter value of the internal clock synchronous counter, the transmission of the next frame is stopped. When the counter values become equal, both the counter values are reset and the next frame is transmitted.