METHOD AND DEVICE FOR DECODING MPEG SIGNAL

Japanese Patent JP2001168728

A

To provide an MPEG video extension method and a device using plural stages interconnected with a 2-wire interface arranged as a pipeline processing machine.

A control token and a data token are delivered to a single 2-wire interface carrying both the control of a token form and data. A token decoding circuit is arranged in a certain stage, certain tokens are recognized as the control token relating to the stage and the unrecognized control token passes through a pipeline. A rearrangement processing circuit is arranged inside a selected stage, responds to the recognized control token and reconstitutes the stage so as to handle an identified data token. The circuits and processing techniques of various original supporting sub-systems for operating a system including memory address specification, data conversion using a common processing block, time synchronization, asynchronous buffering, the storage of video information and a parallel Huffman decoder, etc., are presented.

WISE ADRIAN P (GB)
DEWAR KEVIN D (GB)
JONES ANTHONY MARK (GB)
SOTHERAN MARTIN WILLIAM (GB)
SMITH COLIN (GB)
FINCH HELEN ROSEMARY (GB)
CLAYDON ANTHONY PETER JOHN (GB)
PATTERSON DONALD WILLIAM W (GB)
BARNES MARK (GB)
KULIGOWSKI ANDREW PETER (GB)
ROBBINS WILLIAM P (GB)
BIRCH NICHOLAS (GB)
BARNES DAVID ANDREW (GB)

JP2000226091A

June 22, 2001

July 28, 1995

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DISCOVISION ASS (US)

H04N5/92; G06F3/14; G06F12/00; G06F12/02; G06F12/06; G06F12/08; G06F13/00; G06F13/16; G06F13/28; G06F13/37; G06T9/00; G11B7/00; G11B27/10; H03M7/30; H03M7/40; H03M7/42; H04L7/00; H04L7/08; H04L12/433; H04N7/26; H04N7/32; H04N7/50; H04N7/52; G06F12/04; (IPC1-7): H03M7/42

Fujihiko Motohiko

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