PURPOSE: To shorten the number of cycles of the product-sum operation of a specific value or below by adding the accumulation of the middle partial product to the accumulation of the lower partial product and the accumulation of the upper partial product.

CONSTITUTION: A middle accumulator accM of 40-bit width for accumulating singly the partial product of the upper digit and the lower digit of unit word length data is provided as an accumulator for holding the accumulation of a result of multiplication. Also, this device is provided with a bit shifter BS2 for outputting data M held by this middle accumulator accM as data obtained by shifting it by 16 bits to the higher rank is accordance with a command, the M being as it is, or data obtained by shifting it by 16 bits to the lower direction. In such a way, three processings of a data transfer to a multiplier input register, multiplication for deriving the partial product, and an operation for adding the derived partial product to a result of accumulation on the corresponding accumulator are executed in four cycles, respectively. Accordingly, a processing cycle of a double precision product-sum operation which requires six cycles up to the present can be shortened to four cycles and an arithmetic processing can be executed at a high speed.