To improve the capability of blind-converging an equalizer in spite of the increase of a symbol level by using an output sample from the equalizer.

A circuit 500 includes a central arithmetic processor (processor) 505 and the equalizer 510, which is supposed to be phase dividing FSLE, e.g. The equalizer 510 is supposed to include at least one tap coefficient resistor for storing a value concerning a corresponding tap coefficient vector, e.g. The processor 505 includes a memory for realizing a window MMA type algorithm. An equalizer output signal 511 expressing the sequence of an equalizer output sample is given to the processor 505, which analyzes the signal 511 to adapt the value of a tap coefficient to converge to a right solution.