To simplify a processing procedure and to attain reduction of a hardware circuit scale to be mounted by processing a divided optical signal with a 3 parallel system in serial/parallel converting the signal.
Each signal which is divided into eight is divided into two at a first FEC frame decode part 21 and are made into 16 signals. An optical signal which, is divided into two before is further divided into 8 and are made into 128 signals at a second FEC frame decode part 22. A serial/parallel conversion part 3 at the next step is an assembly of individual serial/parallel conversion part 31 provided in accordance with respective signals. Then, individual serial/parallel conversion part 31 serial/parallel converts the signal divided into 128, and gives them to respective disposed three FEC frame conversion parts 41 to 43. Thus, the signal divided into 128 is divided into three signals through the serial/parallel conversion part 3 and processed.
NOMURA KENICHI
FUJISAWA TAKANORI
HARA YASUSHI
TANAKA HIROAKI
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