Title:
METHOD AND DEVICE FOR PERFORMING REPEATED BLOCK INSTRUCTION BY ZERO CYCLE OVERHEAD ALONG NESTED LOOP
Document Type and Number:
Japanese Patent JP2004005603
Kind Code:
A
Abstract:
To improve the execution of an instruction loop, circuits, systems, and an execution method to increase the signal processing efficiency of a microprocessor.
When a block repetition instruction starts an execution, a present status is stored in a stack, and a stack point maintains the stack. When the block repetition instruction is completed, the stored state is recovered from the stack. The status automatically stored and recovered include a block start address, a block endless address, a present repetition counter, and status information for displaying whether the other block repetition instructions are inputted or not.
Inventors:
EHLIG PETER N
TESSAROLO ALEXANDER
TESSAROLO ALEXANDER
Application Number:
JP2003115827A
Publication Date:
January 08, 2004
Filing Date:
April 21, 2003
Export Citation:
Assignee:
TEXAS INSTRUMENTS INC
International Classes:
G06F9/38; G06F9/00; G06F9/30; G06F9/32; (IPC1-7): G06F9/38; G06F9/32
Attorney, Agent or Firm:
Hideto Asamura
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue
Hajime Asamura
Hayashi Zouzo
Eiichi Sobue