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Title:
METHOD, DEVICE AND PROGRAM FOR SIMULATING CIRCUIT CONTAINING PARTIAL DEPLETION TYPE MOS TRANSISTOR TO BE OPERATED FOR FLOATING IN BODY AREA THEREOF
Document Type and Number:
Japanese Patent JP2003281213
Kind Code:
A
Abstract:

To improve convergence of circuit simulation by appropriately setting the transistor initial condition to improve convergence.

Electrostatic capacitor between each terminal and a body of each partial depletion type MOS transistor to be operated for floating in a body area thereof and contained in a circuit to be simulated is obtained (S3). Body electrical potential in the condition that the transistor is turned on for normal operation is obtained on the basis of a formula of a current balance per each transistor (S4), and initial body change quantity is obtained per each transistor on the basis of a relation formula between the electrostatic capacity, an electrical potential of each terminal and the body potential when the transistor is turned on (S5). The initial current flowing in each terminal of each transistor is set at 0 (S6). The initial potential of each terminal is obtained from a net list, and the initial body potential is decided on the basis of the initial potential and the initial body charge quantity (S7).


Inventors:
TAGAWA YUKIO
Application Number:
JP2002077712A
Publication Date:
October 03, 2003
Filing Date:
March 20, 2002
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F17/50; H01L29/786; (IPC1-7): G06F17/50; H01L29/786
Attorney, Agent or Firm:
Matsumoto Shinkichi