Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
METHOD AND DEVICE FOR PROVIDING ALL DIGITAL LOOP HAVING POWER OPTIMIZATION MODE
Document Type and Number:
Japanese Patent JP2002111900
Kind Code:
A
Abstract:

To provide a device that can be used in an all digital loop having a low power transfer mode without permitting a POTS life line to depend on a switch/bypass circuit and a corresponding line card which is connected to it at the time of transferring a digital sound signal with high speed data.

The all digital loop includes a first network node 30, a second network node 31 and a data transmission line 32 between them. The first and second network nodes 30 and 31 are operable to transmit at least one digitized telephone number with other digital data through the set of carriers. When a power source breaks down in the first network node 30, the first or second network node 30 or 31 includes or is associated with a means which is operable to selectively supply power to the first node 30 in such a way that the first node 30 operates only via the limited subset of the carriers. In the limited subset, power required for transmitting a telephone life line signal between the first node 30 and the second node 31 is suppressed to be minimum.


Inventors:
DE CLERCQ LUC JOSEPHINE T
PLOUMEN FRANCISCUS MARIA
VAN BLADEL MARC MARIA MARCEL
REUSENS PETER P F
VERPOOTEN LUC MARIA MARCEL
VERBIEST WILLEM JULES ANTOINE
Application Number:
JP2001213271A
Publication Date:
April 12, 2002
Filing Date:
July 13, 2001
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
CIT ALCATEL
International Classes:
H04L12/10; H04L12/20; H04M3/00; H04M7/00; H04M11/00; H04M19/00; H04M19/08; H04Q3/42; H04Q11/04; (IPC1-7): H04M11/00; H04L12/10; H04M3/00; H04M7/00; H04Q3/42
Attorney, Agent or Firm:
Yoshio Kawaguchi (1 person outside)