To improve the efficiency of design verification and that of IP (intellectual property).

The system is provided with a verification algorithm generation part 4 and a function design verification part 5 which convert RTL description to a programmable logic and verify whether an algorithm and the RTL description are equivalent to each other or not on the basis of the algorithm and the programmable logic, and a logic design verification part 6 which designs the logic of an integrated circuit on the basis of the RTL description of which the equivalence to the algorithm has been verified by parts 4 and 5.