Title:
METHOD AND DEVICE FOR VERIFYING LAYOUT DESIGN
Document Type and Number:
Japanese Patent JPH0637183
Kind Code:
A
Abstract:
PURPOSE: To improve the efficiency of layer design verification so as to shorten the turnaround time of design development and improve the design development quality.
CONSTITUTION: After a mask layout pattern reading (step 801) and circuit information reading (step 802) are performed, design rule checking(DRC) (step 803), electrical rule checking(ERC) (step 806), counter diffusion checking (step 809), floating gate checking (step 812), layout element collation verification (step 815), layer-versus-circuit diagram collation verification (LVS) (step 818) are successively executed. Whenever an error is found in each step, the mask layout pattern is corrected (in steps 805, 808, 811, 814, 817, and 820).
Inventors:
HASEGAWA JUNKO
YAMADA TOSHIRO
YAMADA TOSHIRO
Application Number:
JP18942192A
Publication Date:
February 10, 1994
Filing Date:
July 16, 1992
Export Citation:
Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H01L21/82; G06F17/50; (IPC1-7): H01L21/82; G06F15/60
Attorney, Agent or Firm:
Hiroshi Maeda (2 outside)