To provide a method of evaluating a solder junction state and to provide chip components for evaluating a solder junction state capable of three-dimensionally recognizing a crack shape, or the like of a solder junction section by accurately grasping and determining the amount of polishing of a specimen and parallelism of a polishing section, improving reliability in observation of the section, and performing observation by setting a plurality of target sections to one observation target.

When observing a junction state of a solder junction section 12, the chip components 11 for evaluation a solder junction state and the solder junction section 12 are polished on a plane A nearly vertical to a first reference line 21. By measuring interval widths b1, b2 between the first reference line 21 and first lines 22, 23 for adjusting the amount of polishing and interval widths b3, b4 between a second reference line 31 and second lines 32, 33 for adjusting the amount of polishing on a section of the chip components 11 for evaluating a solder junction state, parallelism of the section of the chip components 11 for evaluating a solder junction state is confirmed.