Title:
METHOD OF FABRICATING ELECTRIC CONNECTION PACKAGE OF GLASSSCERAMIC*CONDUCTOR
Document Type and Number:
Japanese Patent JPS55128856
Kind Code:
A
Abstract:
A method for fabricating an interconnection package for a plurality of semiconductor chips which include the fabrication of a multi-layered glass-ceramic superstructure with a multi-layered distribution of conductors on a preformed multi-layered glass-ceramic base, by the repeatable steps of depositing a conductor pattern on the base and forming thereon a crystallizable glass dielectric layer which is then crystallized to a glass-ceramic prior to further additions of conductor patterns and crystallizable glass layers to form a monolithic compatible substrate all through. Semiconductor chips can be electrically connected to expose conductor patterns at the top surface of the resultant glass-ceramic package.
Inventors:
BAANTO NAAKEN
RAO RAMAMAHARA TAMARA
RAO RAMAMAHARA TAMARA
Application Number:
JP370680A
Publication Date:
October 06, 1980
Filing Date:
January 18, 1980
Export Citation:
Assignee:
IBM
International Classes:
H01L21/48; H01L23/08; H01L23/15; H01L23/12; H01L23/538; H05K1/11; H05K3/46; H05K1/03; H05K3/10; H05K3/24; H05K3/38; H05K3/42; (IPC1-7): H01L23/08; H01L23/52