Title:
METHOD OF FORMING INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JPS5780743
Kind Code:
A
Abstract:
A method of reducing lateral field oxidation in the vicinity of the active regions of a silicon substrate in which integrated circuit elements are to be formed. Mesas, the tops of which are the active regions, are formed by ion beam etching of the silicon substrate. The mesas are protected by caps of silicon nitride overlying the top and sides of the mesas during field oxide formation. Subsequently the caps of silicon nitride are removed and the exposed sides of the mesas are oxidized to form a thick layer of silicon dioxide contiguous to the mesas.
Inventors:
TATSUTOOSHIINGU POORU CHIYOU
MARIO GETSUZO
MARIO GETSUZO
Application Number:
JP14403681A
Publication Date:
May 20, 1982
Filing Date:
September 14, 1981
Export Citation:
Assignee:
GEN ELECTRIC
International Classes:
H01L21/308; H01L21/316; H01L21/76; H01L21/32; H01L21/762; (IPC1-7): H01L21/76; H01L21/94
Other References:
IBM TECHNICAL DISCLOSURE BULLETIN=1972