Title:
半導体デバイスにおいてアイソレーション膜を形成する方法
Document Type and Number:
Japanese Patent JP4139380
Kind Code:
B2
Abstract:
Disclosed herein are isolation methods for use in semiconductor devices. One example method includes forming a hard mask layer by sequentially stacking a silicon oxide layer, a silicon nitride layer, and a thermal oxide layer on a semiconductor substrate, forming a hard mask layer pattern by patterning the hard mask layer to expose a surface of the semiconductor substrate corresponding to a field area, forming a spacer on each sidewall of the hard mask layer pattern by considering a per-side amount according to the pull-back target, forming a trench in the semiconductor substrate by removing the exposed surface of the semiconductor substrate, filling up the trench with an insulating layer, and removing the hard mask layer pattern and the spacer.
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Inventors:
Shin Moon Jun
Application Number:
JP2004376946A
Publication Date:
August 27, 2008
Filing Date:
December 27, 2004
Export Citation:
Assignee:
Tobu Nanan Semiconductor Co., Ltd.
International Classes:
H01L21/3065; H01L21/76; H01L21/762; H01L21/8242
Domestic Patent References:
| JP11145274A | ||||
| JP2000091418A | ||||
| JP2001237168A | ||||
| JP2001068543A | ||||
| JP11074340A |
Attorney, Agent or Firm:
Sadao Kumakura
Fumiaki Otsuka
Shishido Kaichi
Village shrine Atsuo
Disciple Maru Ken
Ino Sato
Fumiaki Otsuka
Shishido Kaichi
Village shrine Atsuo
Disciple Maru Ken
Ino Sato