Title:
METHOD OF FORMING MULTILAYER WIRING
Document Type and Number:
Japanese Patent JPH0228955
Kind Code:
A
Abstract:
PURPOSE: To obtain a submicron class very large scale integrated circuit and multilayered wiring for very high speed integrated circuit technology, by forming a multilayered interconnection wiring, using many mutually related critical processing steps. CONSTITUTION: The forming method comprises the steps of vacuum evaporating Ti of about 100nm and Al 22 contg. Cu about 0.5-10wt.% and Si about 2.5-8wt.% on a paassivation layer 12 and contact vias to form a first level wiring layer, heating an Si substrate to anneal the first level wiring layer, forming a multilayered passivation layer 28 involving a polymer layer 24 having contact vias which expose at least part of the first level wiring layer on this wiring layer, vacuum evaporating a thin Ti layer 32 on the passivation layer 28 and contact vias 26, and vacuum evaporating a thick metal layer 34 having a different compsn. from that of the metal layer 22 on the Ti layer 32 to form a second level wiring layer.
Inventors:
POORU AARUDEN FUAARAA
ROBAATO MAIKERU GEFUKEN
ROBAATO MAIKERU GEFUKEN
Application Number:
JP2682389A
Publication Date:
January 31, 1990
Filing Date:
February 07, 1989
Export Citation:
Assignee:
IBM
International Classes:
H01L23/52; H01L21/312; H01L21/3205; H01L21/768; H01L23/532; (IPC1-7): H01L21/312; H01L21/3205; H01L21/88; H01L21/90
Domestic Patent References:
| JPS6448447A | 1989-02-22 | |||
| JPS6459937A | 1989-03-07 | |||
| JPS59198734A | 1984-11-10 | |||
| JPS5420681A | 1979-02-16 | |||
| JPS5380966A | 1978-07-17 |
Attorney, Agent or Firm:
Kiyoshi Goda (5 outside)
Next Patent: JPH0228956