Title:
METHOD OF FORMING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3545084
Kind Code:
B2
Abstract:
PURPOSE: To form a low resistance high melting point metal silicide in a self alignment manner without increasing any junction leakage even when an im purity diffusion layer is very shallow.
CONSTITUTION: A poly Si film 16 is formed on a gate oxide film 14 on an Si substrate into which an impurity is ion implanted, and thereafter it is patterned to form a gate electrode 18 on which a SiO2 film is deposited and thereafter a side wall 20 of the gate electrode is formed. Using them as a mask, As is ion-implanted to form an impurity diffusion layer 22 of an S/D region. After a surface oxide film is removed with hydrofluoric acid, a Co film 24 and a TiN film 26 are continuously sputtered. Then, a non-reacted Co film after formation of the CoSi film is removed in a first heat treatment at 550°C for 30 seconds, and a second heat treatment is performed at 750°C for 30 seconds like the prior art to make the CoSi film low resistance. Hereby, when the impurity diffusion layer becomes very shallow, reverse I-V characteristic of a pn junction just under the CoSi film 28 is severely varied, but provided a third heat treatment is performed after the second heat treatment is performed at 80°C for 30 seconds, the variations are sharply reduced to improve the characteristic.
More Like This:
| JPS515966 | HANDOTAISOCHINO SEIZOHOHO |
| JPH05102074 | MOS TRANSISTOR |
| JPH0226032 | MANUFACTURE OF SEMICONDUCTOR DEVICE |
Inventors:
Atsuro Fushida
Application Number:
JP6142195A
Publication Date:
July 21, 2004
Filing Date:
March 20, 1995
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L21/28; (IPC1-7): H01L21/28
Domestic Patent References:
| JP7283168A |
Attorney, Agent or Firm:
Yoshito Kitano
Previous Patent: SYNTHETIC RESIN MADE RACK FOR HOUSING SHOES
Next Patent: BROAD BAND PULSE PATTERN GENERATOR
Next Patent: BROAD BAND PULSE PATTERN GENERATOR