Title:
薄膜構造体の形成方法並びに薄膜構造体、振動センサ、圧力センサ及び加速度センサ
Document Type and Number:
Japanese Patent JP4929753
Kind Code:
B2
Abstract:
A method for forming a thin film structure, which has small tensile stress due to controlled mechanical stress, and is made to be conductive, is provided. A lower film including polysilicon thin film is formed on a substrate such as Si substrate, then an impurity such as P is doped into the lower film and thermally diffused, thereby the lower film is made conductive. Then, an upper film is deposited on the lower film, the upper film including a polysilicon thin film that is simply deposited and not made to be conductive. The upper film has a tensile stress in an approximately the same level as compressive stress of the lower film, and a thin film structure as a whole, the structure including the lower film and the upper film, is adjusted to have small tensile stress.
Inventors:
Takashi Kasai
Shuichi Wakabayashi
Shuichi Wakabayashi
Application Number:
JP2006044870A
Publication Date:
May 09, 2012
Filing Date:
February 22, 2006
Export Citation:
Assignee:
OMRON Corporation
International Classes:
G01H11/06; B81B3/00; B81C1/00; G01C19/56; G01C19/574; G01C19/5769; G01L9/00; G01P15/125; H01L29/84; H04R19/04; H04R31/00
Domestic Patent References:
| JP10111195A | ||||
| JP7030128A |
Foreign References:
| US6686637 | ||||
| US6967757 |
Other References:
AGARWAL A ET AL, "A process technique to engineer the stress of thick doped polysilicon films for mems applications",PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS, 2002. IPFA 2002. PROCEEDINGS OF THE 9TH INTERNATIONAL SYMPOSIUM ON THE 8-12 JULY 2002, PISCATAWAY, NJ, USA,IEEE,米国,2002年 7月 8日,pages 207-211
Attorney, Agent or Firm:
Masafusa Nakano