Title:
METHOD OF MAKING ALL SURFACES OF WAFER FOR INTEGRATED CIRCUIT DEVICE GLOBAL PLANE OR FLATTENING IT
Document Type and Number:
Japanese Patent JPH08236526
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To avoid the resolution problem of a void and photolithography in a dielectric material by patterning an etching mask layer arranged on a packing layer covering a structure on a wafer surface by lithography, and etching the packing layer. SOLUTION: At the time of globally planarizing a wafer 10 having a plurality of structures forming high topography and low topography, a filling layer 42 is arranged across the surface of the wafer 10 so that the structure can be covered. Next, an etching mask layer 44 is arranged across the surface of the filling layer 42, and an opening is formed in the etching mask layer 44, the area of the filling layer 42 for etching is exposed, and the etching of the exposed area of the filling layer 42 is carried out. Then, a second surface having topography substantially a little higher than defined high topography is provided on the surface of the wafer 10. Then, the high topography of the second surface is removed so that the planarized wafer surface can be obtained.
Inventors:
MATEIASU ERU PESHIYUKE
RAINHARUTO YOTSUTO SHIYUTENGUR
RAINHARUTO YOTSUTO SHIYUTENGUR
Application Number:
JP33534295A
Publication Date:
September 13, 1996
Filing Date:
December 22, 1995
Export Citation:
Assignee:
SIEMENS AG
International Classes:
H01L21/31; H01L21/304; H01L21/3105; H01L21/316; H01L21/318; H01L21/3205; (IPC1-7): H01L21/3205; H01L21/304; H01L21/31; H01L21/316; H01L21/318
Domestic Patent References:
| JPH03116753A | 1991-05-17 | |||
| JPH06318583A | 1994-11-15 | |||
| JPS5629326A | 1981-03-24 | |||
| JPH0297951A | 1990-04-10 |
Foreign References:
| EP0341898A2 | 1989-11-15 |
Attorney, Agent or Firm:
Toshio Yano (1 outside)