METHOD OF MANUFACTURING EIFLD EFFECT TRANSISTOR

Title:

METHOD OF MANUFACTURING EIFLD EFFECT TRANSISTOR

Document Type and Number:

Japanese Patent JP2001210658

Kind Code:

A

Abstract:

To provide the simple manufacturing method of the field effect transistor(FET) of a short gate, which uses a compound semiconductor.

An active layer 2 and a contact layer 3 of a first conductive compound semiconductor layer are eptaxially grown sequentially on the substrate 1 of semi-insulation property, which is formed of a compound semiconductor material. Then, a recess 4 is formed. A surface-reforming layer 5 is formed on the surface of the active layer 2 and the contact layer 3. The surface- reforming layer 5 is opened by an electron beam 12. A lower gate electrode 7 is selectively grown in an opening part 6, in a columnar shape with the surface reforming layer 5 as a mask. An insulating film 13 is deposited and planarized. The upper end of the lower gate electrode 7 is exposed. An upper gate electrode 8 connected to the upper end is formed, and an opening extending to the contact layer 3 is formed in the insulating film 13. An ohmic electrode is formed in an opening part 10, and FET is manufactured.

Inventors:

MIYOSHI YOSUKE

Application Number:

JP2000016887A

Publication Date:

August 03, 2001

Filing Date:

January 26, 2000

Export Citation:

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Assignee:

NEC CORP

International Classes:

H01L29/812; H01L21/28; H01L21/338; (IPC1-7): H01L21/338; H01L21/28; H01L29/812

Attorney, Agent or Firm:

Naoki Kyomoto (2 outside)

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