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Patent Searching and Data


Title:
METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP2003124310
Kind Code:
A
Abstract:

To make the surface of an insulation film, forming a resist layer for forming a wiring trench, hydrophobic in a dual damascene method in order to improve adhesion tightness and avoid the separation of the resist layer.

A lower layer wiring layer 6 comprising a barrier metal layer 4 and a metal wiring layer 5 is formed in a lower layer wiring trench 3 formed in a lower layer insulation film 2 on a semiconductor substrate 1. Then, after a protective insulation film 7 and an upper layer insulation film 8 are formed on the substrate, a contact hole 8a is formed in the upper layer insulation film 8. Then, the surface of the upper layer insulation film 8 is washed by an amine- system chemical solution. Then, the surface is washed by deionized water for ten minutes or longer to remove the amine-system chemical solution. Then, the upper layer insulation film 8 is etched by a resist layer 12 having an opening 12a including the contact hole 8a as a mask to form an upper layer wiring trench 8b connected with the contact hole 8a. Then, an upper layer wiring layer 15 comprising a barrier metal layer 13 and a metal wiring layer 14 is formed.


Inventors:
SEO AKIRA
Application Number:
JP2001314893A
Publication Date:
April 25, 2003
Filing Date:
October 12, 2001
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G03F7/16; B05D3/10; B05D7/00; H01L21/027; H01L21/308; H01L21/768; (IPC1-7): H01L21/768; B05D3/10; B05D7/00; G03F7/16; H01L21/027; H01L21/308
Attorney, Agent or Firm:
Fumio Iwahashi (2 others)