Title:
半導体素子の製造方法
Document Type and Number:
Japanese Patent JP7363193
Kind Code:
B2
Abstract:
A method for producing a semiconductor device includes a step of bonding a chip to a SOI wafer, the chip being formed of a III-V group compound semiconductor and including a substrate and a first semiconductor layer; and a step of removing the substrate and the first semiconductor layer from the chip after the step of bonding. In the producing method, the first semiconductor layer has a tensile strain, and the SOI wafer and the chip are heated to a first temperature in the step of bonding, and are cooled to a second temperature lower than the first temperature after the step of bonding.
Inventors:
Takehiko Kikuchi
Hideki Yagi
Nobuhiko Nishiyama
Hideki Yagi
Nobuhiko Nishiyama
Application Number:
JP2019153759A
Publication Date:
October 18, 2023
Filing Date:
August 26, 2019
Export Citation:
Assignee:
Sumitomo Electric Industries, Ltd.
International Classes:
H01S5/026; H01S5/343
Domestic Patent References:
| JP2015164148A | ||||
| JP7273402A | ||||
| JP2015179783A | ||||
| JP2002015965A | ||||
| JP2015156440A | ||||
| JP2016001681A | ||||
| JP2014003105A | ||||
| JP2013021023A | ||||
| JP2009006521A | ||||
| JP2006114847A | ||||
| JP2003119100A | ||||
| JP8316442A | ||||
| JP6267804A |
Foreign References:
| WO2013187079A1 | ||||
| US20180082960 | ||||
| US20140145587 | ||||
| CN102067284A |
Attorney, Agent or Firm:
Shuhei Katayama