METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Title:

METHOD FOR MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND THE SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Document Type and Number:

Japanese Patent JP2002050696

Kind Code:

A

Abstract:

To eliminate unbalance of characteristics due to charge up at dry etching of a pair transistor which consists of two transistors.

First metal wirings 10 and 14 of first and second transistors connected, respectively, with first and second gates 4 and 6 constituting a pair transistor are connected, with first and second P-type diffusion layers 7 and 11, respectively. Since incident ion charges escape through the first and second P-type diffusion layers 7 and 11 at dry etching for the formation of the metal wirings, charge up will not take place on the first and second gate electrodes 4 and 6 or the characteristics will not become unbalanced by charge up and thereby no difference appears in the characteristics between transistors. Consequently, a sense amplifier for use in an operational amplifier, the memory cell of an SRAM or a storage device having high sensitivity characteristics can be provided.

Inventors:

FUJII TOYOKAZU
FUKUMOTO AKIRA
ISHIBASHI KENSAKU

Application Number:

JP2000233787A

Publication Date:

February 15, 2002

Filing Date:

August 02, 2000

Export Citation:

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Assignee:

MATSUSHITA ELECTRIC IND CO LTD

International Classes:

H01L21/302; H01L21/3065; H01L21/3213; H01L21/8234; H01L21/8244; H01L27/088; H01L27/11; (IPC1-7): H01L21/8234; H01L27/088; H01L21/3065; H01L21/3213; H01L21/8244; H01L27/11

Attorney, Agent or Firm:

Yoshihiro Morimoto

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