To reduce irregularities in the plane of sheet resistance of a semiconductor substrate generated due to thermal diffusion.
If the semiconductor substrate 1 is disposed in vertical placement so as to be subjected to thermal diffusion in a diffusion furnace, the sheet resistance of an upper side 7 of the semiconductor substrate 1 become lower than the sheet resistance of a lower side 8 so that the irregularities in the plane of sheet resistance are generated. After the thermal diffusion, when etching performs a pn junction isolation by using a substrate surface treatment apparatus, the semiconductor substrate 1 is installed in a conveyance roller 6 so that the upper side 7 of the semiconductor substrate 1 may turn to the up-stream conveyance direction. The semiconductor substrate 1 is etched while being conveyed and then an unnecessary n layer is removed. Since etching quantity of the upper side 7 of the semiconductor substrate 1 used as the back end increases more than a head when being conveyed, the sheet resistance of the upper side 7 of the semiconductor substrate 1 increases, and thus the irregularities reduces in the plane of the sheet resistance.
TANAKA SATOSHI
Shuzo Hinode
Seiji Goto
Junko Ohara