Title:
METHOD OF MANUFACTURING WAFER-LEVEL VACUUM PACKAGED DEVICE
Document Type and Number:
Japanese Patent JP2008132587
Kind Code:
A
Abstract:
To inexpensively provide a package where a base board and a MEMS device are fitted in a housing at a low cost.
A device layer having one or more than that of Micro Electro-Mechanical Systems (MEMS) devices is bonded in a first surface to a first wafer. The first wafer has one or more than that of silicon pins 32 for electric conductivity, and electrically connects the silicon pins and the device layer. A second wafer having similarly one or more than that of silicon pins, is bonded to a second surface being an opposite surface of the first surface of the device layer. The first and second wafers are made of boro-slicate glass, and the device layer is made of silicon.
Inventors:
ESKRIDGE MARK H
JAFRI IJAZ H
JAFRI IJAZ H
Application Number:
JP2007204178A
Publication Date:
June 12, 2008
Filing Date:
August 06, 2007
Export Citation:
Assignee:
HONEYWELL INT INC
International Classes:
B81B1/00; B81C3/00; H01L23/02; H01L23/26
Domestic Patent References:
| JP2004071481A | 2004-03-04 | |||
| JP2006513046A | 2006-04-20 |
Foreign References:
| WO2005102911A1 | 2005-11-03 |
Attorney, Agent or Firm:
Kazuo Shamoto
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Naoki Kazuma
Shinjiro Ono
Yasushi Kobayashi
Akio Chiba
Hiroyuki Tomita
Naoki Kazuma
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