Title:
METHOD FOR MANUFACTURING WIRING BOARD
Document Type and Number:
Japanese Patent JP2016028420
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a method for manufacturing a wiring board by which a resin can be filled in a gap between conductor patterns of 100 μm or more in thickness while suppressing the void creation.SOLUTION: A method for manufacturing a wiring board comprises the steps of: preparing a core material having an insulator layer and a conductor pattern; preparing one or more prepregs, each including glass cloth and first and second resin layers covering the glass cloth on opposing sides respectively and made of a semi-hardened resin impregnated into the glass cloth; forming a laminate by putting the one or more prepregs on each other so that one of the one or more prepregs covers the conductor pattern and is provided on the surface of the insulator layer of the core material; and heating the laminate while applying a pressure thereto. The aperture ratio of the glass cloth is 3-15%. The thickness t of the first and second resin layers, the percentage a(%) of the area of the conductor pattern to the area of the surface of the insulator layer of the core material, the thickness T of the conductor pattern, and the number n of the one or more prepregs satisfy the relation given by: T≥100 (μm) and t<(1-a/100)×T<2×n×t.SELECTED DRAWING: Figure 1
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Inventors:
SUZUKI FUMITO
ISHIDA TAKEHIRO
ISHIDA TAKEHIRO
Application Number:
JP2015135652A
Publication Date:
February 25, 2016
Filing Date:
July 06, 2015
Export Citation:
Assignee:
PANASONIC IP MAN CORP
International Classes:
H05K3/46; B32B5/28; B32B17/04; H05K1/03
Domestic Patent References:
| JP2000226752A | 2000-08-15 | |||
| JPH11114956A | 1999-04-27 | |||
| JP2003031957A | 2003-01-31 | |||
| JPH0818179A | 1996-01-19 | |||
| JP2003093957A | 2003-04-02 |
Attorney, Agent or Firm:
Keisei Nishikawa
Mizuhiji Katsuhisa
Yoshishige Takeo
Kyohei Tokioka
Mizuhiji Katsuhisa
Yoshishige Takeo
Kyohei Tokioka