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Title:
METHOD FOR MOUNTING BARE CHIP
Document Type and Number:
Japanese Patent JPH05235242
Kind Code:
A
Abstract:

PURPOSE: To reduce the mounting area, to facilitate an inspection of a connected part and to strengthen against heat cycle by cutting inner leads of a bare chip at a position slightly protruding from an outer periphery of the chip, and connecting protruding ends of the leads to a pattern on a board.

CONSTITUTION: Inner leads 2 brought at one ends into pressure contact with an Au bump 5 of a chip 4 are held by a carrier tape 1, and cut at a position of about 0.5mm from an outer periphery of the chip 4 by using a laser. As a result, the chip 4 becomes a state that a plurality of the leads 2 protrude about 0.5mm from the outer periphery of the chip 4. Then, the leads 2 are formed on a board 6, aligned with a Cu pattern 7 coated with precoating solder 8, and mounted. The solder 8 reflows to connect the leads 2 to the pattern 7. Thus, the mounting area can be reduced, the inspection of the connected part is facilitated, its strength becomes strong against heat cycle, and the cutting positional accuracy is improved without damaging the chip.


Inventors:
TANIGUCHI YOSHIKUNI
SOGO KEIKO
Application Number:
JP7265692A
Publication Date:
September 10, 1993
Filing Date:
February 21, 1992
Export Citation:
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Assignee:
SONY CORP
International Classes:
B23K26/38; H01L23/50; (IPC1-7): H01L23/50; B23K26/00
Attorney, Agent or Firm:
Yoshio Inamoto (1 outside)



 
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