Title:
METHOD OF NOISE REDUCTION IN PHASE LOCKED LOOP FREQUENCY SYNTHESIZATION
Document Type and Number:
Japanese Patent JPH0730417
Kind Code:
A
Abstract:
PURPOSE: To shorten a frequency settling time and to reduce noise in the method for reducing noise at the time of synthesizing phase locked loop frequency in a communication field. CONSTITUTION: A phase locked loop circuit including 1st and 2nd counting means 10, 14 connected to 1st and 2nd registers 18, 20 is disclosed. The 1st register 18 stores a number M and the 2nd register 20 stores a number N. The 1st counting means 10 outputs an output signal F1 in response to the M cycles of a reference signal Fref and the 2nd counting means 14 outputs an output signal F2 in response to the N cycles of an output signal Fout. The signals F1, F2, Fref, Fout are connected to a phase detector 30 and the phase of the signal Fref is compared with that of the signal Fout. An output signal from the detector 30 is connected to a voltage controlled oscillator 12 for generating a signal Fout proportional to the output signal of the detector 30. The signal Fout is fed back to the 2nd register 20 until the phase locked loop circuit is settled.
Inventors:
BEIJIYOO SAKARI KOONEN
Application Number:
JP11260194A
Publication Date:
January 31, 1995
Filing Date:
May 26, 1994
Export Citation:
Assignee:
NOKIA MOBILE PHONES LTD
International Classes:
H03L7/089; H03L7/18; H03L7/193; H03L7/199; (IPC1-7): H03L7/18; H03L7/199
Attorney, Agent or Firm:
Takashi Ishida (3 others)
Next Patent: FREQUENCY SYNTHESIZER