PURPOSE: To speed up partial writing in main memory by providing the main memory with the function that when writing data having a pit width of less than error detecting unit, writes particular composite data in the main memory.

CONSTITUTION: If during the execution of partial writing in a main memory 01, data corresponding to an address subject to writing in the main memory 01 exists in a cache memory 02, data in the cache memory 02 is read out without making read operation of the main memory 01, the data read out is put together with new partially written data, and this composite data is written in the main memory 01 in error detecting unit. Read operation of cache memory 02 is usually much faster than that of the main memory 01. With this, the requirement for partial writing from the processor to the main memory is executed by replacing it with writing operation to the main memory in error detecting unit without considerable delay.