Title:
METHOD FOR PATTERNING LACQUER LAYER TO HOLD ELECTRICAL GRID LINES
Document Type and Number:
Japanese Patent JP2012216782
Kind Code:
A
Abstract:
To provide a method for simultaneously forming functional light structures and grooves configured to hold electrical circuitry on a lacquer layer deposited on a base substrate for use in an optoelectronic device.
The method includes applying a lacquer layer 203 onto a base substrate 202, and using a stamper to replicate grooves 206 and functional light structures 204 simultaneously onto the lacquer layer 203. The stamper has a mating surface, which has negative impressions of the grooves on its first portion and the functional light structures on its second portion. The functional light structures 204 are provided to enable light trapping or light extraction. Thereafter, electrical circuitry 208 is formed in the grooves 206.
Inventors:
JAN MATTHIJS TER MEULEN
PATRICK PETERS
PATRICK PETERS
Application Number:
JP2012049288A
Publication Date:
November 08, 2012
Filing Date:
March 06, 2012
Export Citation:
Assignee:
MOSER BAER INDIA LTD
International Classes:
H05K3/10; H01L51/42; H01L51/50; H05B33/02; H05B33/10; H05B44/00
Attorney, Agent or Firm:
sk patent corporation
Akihiko Okuno
Hiroyuki Ito
Akihiko Okuno
Hiroyuki Ito