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Patent Searching and Data


Title:
METHOD FOR PREVENTING CONSUMPTION OF TIME TO PROGRAM ADDRESS IN DEFECTIVE COLUMN
Document Type and Number:
Japanese Patent JP2008310955
Kind Code:
A
Abstract:

To provide a method for preventing consumption of time to program a defective column.

This method includes: (a) a step in which a TAG RAM address-specified by the same address 30 as that applied to a memory to be tested is established; (b) a step in which it is discriminated that an applied address is related to a defective column; (c) a step in which displays 123, 124 indicating that the column is defective are stored in the applied address in the tag RAM; (d) a step in which an automatic data replacement mechanism (35") is enabled during the next step of the test of the memory to be tested after (a) to (c); (e1) a step in which programming the memory to be tested for the test address is tried applying the test address for the tag RAM; and (e2) a step in which a value of data to be programmed is replaced by informing directly that the memory to be tested is normal when the tag RAM contains the display indicating that the test address belong to a defective column.


Inventors:
KRECH JR ALAN S
FREESEMAN JOHN M
LAI KEN HANH DUC
Application Number:
JP2008214834A
Publication Date:
December 25, 2008
Filing Date:
August 25, 2008
Export Citation:
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Assignee:
VERIGY PTE LTD SINGAPORE
International Classes:
G01R31/28; G11C29/56; G06F12/16; G11C16/02
Attorney, Agent or Firm:
Shoichi Okuyama
Arihara Koichi
Matsushima Tetsuo
Hidefumi Kawamura