Title:
METHOD OF PRODUCING C-MOS SEMICONDUCTOR
Document Type and Number:
Japanese Patent JPS5878453
Kind Code:
A
Abstract:
An improved process is provided for fabricating CMOS (Complementary Metal Oxide Semiconductor) devices formed on a semiconductor substrate having n-channel and p-channel regions of n- and p-type conductivity, respectively. Conventional source, drain and gate portions are formed in the regions and electrical contacts are made thereto. The improvement comprises providing self-aligned channel stops between regions of the same conductivity and between regions of the opposite conductivity. The channel stops between regions of the opposite conductivity are mutually self-aligned. The self-alignment is achieved by use of a single mask, called a "complementary" mask. The process of the invention permits fabrication of submicrometer devices.
Inventors:
JIYON WAI CHIEN
Application Number:
JP15016482A
Publication Date:
May 12, 1983
Filing Date:
August 31, 1982
Export Citation:
Assignee:
HUGHES AIRCRAFT CO
International Classes:
H01L27/08; H01L21/8238; H01L27/092; H01L29/06; H01L29/78; (IPC1-7): H01L27/08; H01L29/78
Domestic Patent References:
| JPS5270779A | 1977-06-13 | |||
| JPS52143782A | 1977-11-30 | |||
| JPS5691461A | 1981-07-24 |
Attorney, Agent or Firm:
Takehiko Suzue