Title:
METHOD OF PRODUCING INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JPS6052046
Kind Code:
A
Abstract:
A method for manufacturing an integrated circuit thermal print head is illustrated including transistor 20 and a resistor doped region 22 formed on a first surface of a silicon circuit wafer 10. A contamination barrier in the form of a moat 26 filled with silicon nitride 30 is formed around the transistor 20. A support wafer 50 is secured to the first surface of the circuit wafer 10 by an adhesive layer 58. The circuit wafer 10 is thinned, and the exposed surface of the circuit wafer 10 is photoshaped to define wafer segments 68 positioned over the resistor doped region 22.
Inventors:
REIMONDO AARU KURISUCHIYAN
HARII SUU
JIYOSEFU SHII ZAACHIYAA
HARII SUU
JIYOSEFU SHII ZAACHIYAA
Application Number:
JP13120684A
Publication Date:
March 23, 1985
Filing Date:
June 27, 1984
Export Citation:
Assignee:
TELETYPE CORP
International Classes:
B41J2/34; B41J2/355; H01L21/02; H01L21/301; H01L21/52; H01L21/58; H01L21/822; H01L23/14; H01L27/04; H01L27/12; (IPC1-7): B41J3/20; H01L21/58; H01L21/78; H01L23/02; H01L23/12; H01L27/04
Domestic Patent References:
| JPS5717158A | 1982-01-28 | |||
| JPS5387163A | 1978-08-01 | |||
| JPS5893345A | 1983-06-03 | |||
| JPS5459083A | 1979-05-12 | |||
| JPS5283070A | 1977-07-11 | |||
| JPS5745254A | 1982-03-15 |
Attorney, Agent or Firm:
Masao Okabe