To inhibit an attack to the security function of circuit arrangement.

In this method of protecting the circuit arrangement for data processing, particularly a microprocessor, preferably a smart card controller, for the purpose of a manufacture control scanning test at least either during the manufacture or at the completion of the circuit arrangement, the memory cells of the circuit arrangement. The shift register chain of which is preferably a flip-flop, are combined to generate arbitrary states in the memory cells in the circuit arrangement using the shift register chain and the other shift register chain formed in prescribed shape in the circuit arrangement from these memory cells. These states are evaluated by a prescribed method in order to test the functional capacity of the memory cells of the circuit arrangement loaded with these states. After the completion of the manufacture control scanning test, the shift register becomes nonusable.