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Title:
METHOD OF REDUCING NOISE IN SWITCHED CAPACITOR POWER CIRCUIT, AND SWITCHING POWER SOURCE
Document Type and Number:
Japanese Patent JP2004254422
Kind Code:
A
Abstract:

To obtain an output voltage having little distortion using small circuit scale.

A transducing unit 100 includes a plurality of converters 30-3R each having (N×M) pieces of capacitors Ck, 11-Ck, and NM which are connected in series every each M piece. These are controlled by first to fifth power switches Sk, 11-Sk, 4NM, Sk, and 51, connected freely to input terminals and output terminals, and rectify DC input voltages in order prior to be supplied to an output circuit 40. In the output circuit 40, outputs of the plurality of converters are made equal, and further inverted periodically, and the circuit outputs an AC voltage Vout(t). The first to fifth power switches Sk, 11-Sk, and 51 are driven by clock pulses ij which are pulse-modulated based on random signals Ci(t) from a chaos generating circuit 20, whereby switching noise is reduced.


Inventors:
UENO FUMIO
EGUCHI HIROSHI
OTA ICHIRO
INOUE TAKAHIRO
Application Number:
JP2003042112A
Publication Date:
September 09, 2004
Filing Date:
February 20, 2003
Export Citation:
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Assignee:
UENO FUMIO
EGUCHI HIROSHI
OTA ICHIRO
INOUE TAKAHIRO
International Classes:
H02M3/07; H03H19/00; (IPC1-7): H02M3/07; H03H19/00
Attorney, Agent or Firm:
Anami Kensaku



 
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