Title:
メモリデバイスにおけるプログラム撹乱低減方法およびそれを利用するメモリデバイス
Document Type and Number:
Japanese Patent JP7132444
Kind Code:
B2
Abstract:
A memory device includes bit lines, and a cell array including strings, each of which includes memory cells, a select cell coupled to a respective one of the bit lines, and a dummy cell between the select cell and the memory cells. The memory device also includes a select line coupled to the select cells, a dummy word line coupled to the dummy cells, word lines each coupled to a respective row of the memory cells, and a controller coupled to the cell array. The controller is configured to drive a voltage on the dummy word line from a first level to a second level lower than the first level. The controller is also configured to drive a voltage on the select line from the first level to the second level, such that the voltage on the select line reaches the second level after the voltage on the dummy word line reaches the second level. The controller is further configured to, after the voltage on the select line reaches the second level, drive a voltage on a selected word line of the word lines from the second level to a third level higher than the first level to program the memory cells coupled to the selected word line.
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Inventors:
Li Shan
Yo Kai Kai
Twi-in
Jia Jian Quan
Li Kai Wei
Chang An
Yo Kai Kai
Twi-in
Jia Jian Quan
Li Kai Wei
Chang An
Application Number:
JP2021549875A
Publication Date:
September 06, 2022
Filing Date:
December 09, 2019
Export Citation:
Assignee:
Yangtze Memory Technologies Co.,Ltd.
International Classes:
G11C16/10; G11C16/04
Domestic Patent References:
| JP2019109952A |
Foreign References:
| US20190371394 | ||||
| US20190108883 |
Attorney, Agent or Firm:
Hiroi Arai
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