Title:
METHOD AND SYSTEM IN MEMORY DEVICE
Document Type and Number:
Japanese Patent JP2013165282
Kind Code:
A
Abstract:
To mount a ZnCdS switching device on an FPGA circuit and provide an overcurrent programming scheme therefor.
A cross-sectional schematic diagram 29a of a crosspoint device 25 is implemented using a single additional metal layer M3. A ZnCdS switching device is included in a selection layer of an FPGA circuit (in an intermediate part or between a plurality of selection layers), and hence can be provided on the FPGA circuit. This structure reduces the overall size of the FPGA circuit. Further, a ZnCdS switching device may be mounted on another adjacent FPGA circuit. A ZnCdS switching device for an FPGA application can be programmed using an overcurrent programming scheme.
Inventors:
FUJITA SHINOBU
Application Number:
JP2013076082A
Publication Date:
August 22, 2013
Filing Date:
April 01, 2013
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H01L21/82; H01L27/105; H01L45/00; H01L49/00
Domestic Patent References:
| JP2006319028A | 2006-11-24 | |||
| JP2001237380A | 2001-08-31 |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
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