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Title:
METHOD AND SYSTEM FOR RESULT FAULT DETECTION
Document Type and Number:
Japanese Patent JP2003248590
Kind Code:
A
Abstract:

To detect faulty rewriting to a memory space capable of generating for all multi-task scheduling selectable to a transaction with a plurality of sleds.

A task-table generating mechanism 101 in a system 117 requests the execution of the transaction (TR) 109 to an OS system 112, and collects memory access information 102 only of the TR 109, and prepares a task table 103 by pulling out task information. A schedule generating mechanism 104 prepares a schedule table 105 at the basis of the task table 103. Then, a decision mechanism 106 again requests execution of the TR 109 to the OS system, and an interruption control routine 107 performs scheduling at the basis of scheduling of the table 105 while interrupting a scheduler 113 of the OS system. During the operation, a result comparison routine 108 decides whether or not values stored in the memory space, which is objectives of watching to be accessed by the task, are faulty compared with values of the information 102 of the task obtained when first executed the TR 109.


Inventors:
TANAKA AKIYOSHI
FUJIWARA YOJI
ISHIGAKI TSUTOMU
Application Number:
JP2002045711A
Publication Date:
September 05, 2003
Filing Date:
February 22, 2002
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F11/30; G06F9/46; G06F9/48; (IPC1-7): G06F9/46; G06F11/30
Attorney, Agent or Firm:
Osamu Ito (1 person outside)