Title:
METHOD FOR TESTING FUNCTION OF MEMORY CELL OF INTEGRATED MEMORY AND INTEGRATED MEMORY
Document Type and Number:
Japanese Patent JP3563362
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To miniaturize addresses of a memory cell having errors.
SOLUTION: A counter forming a first address part and an another counter forming a second address part have respectively a control input side, also connected to an output side of an addressing unit, each address part of a memory cell to be tested can be taken out at an output side of each counter, a counter addressing a memory cell to be tested is driven, memory cells of intersection regions of one column line group and one row line group are successively addressed, successively memory cells of the other row line group or memory cells of the other column line group are addressed.
Inventors:
Wilfried Dane
Wolfgang Hellfer
Wolfgang Hellfer
Application Number:
JP2001106112A
Publication Date:
September 08, 2004
Filing Date:
April 04, 2001
Export Citation:
Assignee:
Infineon Technolgies SC300 GmbH & Co.KG
International Classes:
G01R31/28; G11C29/00; G11C29/12; G11C29/44; G11C29/10; (IPC1-7): G11C29/00; G01R31/28
Domestic Patent References:
| JP10074397A | ||||
| JP11213700A |
Attorney, Agent or Firm:
Toshio Yano
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel
Toshiomi Yamazaki
Takuya Kuno
Einzel Felix-Reinhard
Reinhard Einsel
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