Title:
METHOD FOR TESTING IC DEVICE ELECTRICALLY
Document Type and Number:
Japanese Patent JP3782293
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a tester for testing individual IC devices or wafers in which a pressure required for bringing all solder bumps in an IC array into contact with a test array can be reduced significantly.
SOLUTION: The tester has a flat test bed comprising a socket array for containing an IC solder ball array and the socket in the test bed has a sidewall directing inward. Consequently, the socket has a sharp edge touching the solder bump array contrary to the flat or dish-like surface at a conventional recess. Since deformation required for bringing all solder bumps in the array into reliable contact with a test array can be reduced significantly, a force required for causing deformation can be reduced correspondingly.
Inventors:
Louis Nelson Earlquist
Inon de Crab
Jericho Jay Jakara
Dean Paul Cosivez
King El. Thailand
Inon de Crab
Jericho Jay Jakara
Dean Paul Cosivez
King El. Thailand
Application Number:
JP2000233853A
Publication Date:
June 07, 2006
Filing Date:
August 02, 2000
Export Citation:
Assignee:
Lucent Technologies, Inc.
International Classes:
G01R31/26; G01R1/073; G01R31/28; H01L21/66; H05K3/34; (IPC1-7): G01R31/26; G01R1/073; G01R31/28; //H05K3/34
Domestic Patent References:
| JP10032070A | ||||
| JP9283880A | ||||
| JP6090076A |
Attorney, Agent or Firm:
Masao Okabe
Hirofumi Mimata
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa
Hirofumi Mimata
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa
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