Title:
METHOD FOR TESTING LIFE OF GATE INSULATION FILM IN SEMICONDUCTOR DEVICE
Document Type and Number:
Japanese Patent JP3230483
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To accurately predict a life of an extremely thin gate-insulation film wherein a direct tunnel current flows by making a gate voltage satisfy a specific expression.
SOLUTION: A gate electrode 3 is provided to a gate oxide film 2 formed in a surface of a P-type Si board 1. The gate oxide film 2 is extremely thin and a direct tunnel current flows when a gate voltage is applied to the gate electrode 3. In the life test method of the gate oxide film 2, Vg is selected to satisfy the condition of an expression: Vo≤Vox≤&phiv b, wherein Vg is a gate voltage, &phiv b is an energy barrier height decided by combination of the P-type Si board 1 and the gate oxide film 2, and Vo is an operational voltage of the P-type Si board 1 with the gate oxide film 2. Therefore, it is possible to carry out a life test by the same leak current mechanism as that during operation of an actual LSI. Thereby, a life can be accurately predicted.
Inventors:
Susumu Koyama
Application Number:
JP8083898A
Publication Date:
November 19, 2001
Filing Date:
March 27, 1998
Export Citation:
Assignee:
NEC
International Classes:
H01L29/78; G01N27/00; H01L21/66; (IPC1-7): H01L21/66; G01N27/00; H01L29/78
Domestic Patent References:
| JP9326429A |
Attorney, Agent or Firm:
Yukio Nishimura