Title:
METHOD TO REMOVE III-V MATERIAL IN HIGH ASPECT RATIO STRUCTURE
Document Type and Number:
Japanese Patent JP2019192913
Kind Code:
A
Abstract:
To solve such a problem that a method for forming a semiconductor device, such as FinFETs, suffers from challenges including difficulty in reaching the bottom of trenches (<30 nm) in high aspect ratio structures, thermal budget limitations, and arsenic contamination and abatement constraints for a substrate processing chamber.SOLUTION: A fin structure processing method includes the steps of: removing a portion of a first fin of a plurality of fins formed on a substrate to expose a surface of a remaining portion of the first fin, the fins being adjacent to dielectric material structures formed on the substrate; performing a deposition operation to form features on the surface of the remaining portion of the first fin by depositing a Group III-V semiconductor material in a substrate processing environment; and performing an etching operation to etch the features with an etching gas to form a plurality of openings between adjacent dielectric material structures, the etching operation being performed in the same chamber as the deposition operation.SELECTED DRAWING: Figure 4A
Inventors:
BAO XINYU
ZHANG YING
ZHOU QINGJUN
LIN YUNG-CHEN
ZHANG YING
ZHOU QINGJUN
LIN YUNG-CHEN
Application Number:
JP2019081708A
Publication Date:
October 31, 2019
Filing Date:
April 23, 2019
Export Citation:
Assignee:
APPLIED MATERIALS INC
International Classes:
H01L21/336; H01L21/205; H01L21/3065; H01L21/31; H01L29/78
Attorney, Agent or Firm:
Yoshiaki Anzai