To improve performance in a system using many symbol levels in a signal space by converging the set of tap coefficient values as the function of the coordinate value of a corresponding area and an output sample.

A circuit 500 comprises a processor 505 and an equalizer 510. The equalizer 510 is a phase division FSLE, for instance, and the equalizer 510 is provided with one tap coefficient register for storing a value for a corresponding tap coefficient vector, for instance. The processor 505 is provided with a memory for realizing multi-modulus algorithm and equalizer output signals 511 for indicating the sequence of equalizer output samples are supplied to the processor 505. The processor 505 analyzes the equalizer output signals 511 so as to adapt the value of the tap coefficient so as to be converged into a correct solution. In such a manner, the blind convergence of the equalizer 510 to become difficult in the case where the number of the symbol levels is increased is made possible.