Title:
DC-DCコンバータにおける電力効率を最適化する方法および回路
Document Type and Number:
Japanese Patent JP4527480
Kind Code:
B2
Abstract:
In one embodiment, a turn-on delay control structure ( 30 ) includes a sense FET device ( 31 ) that is coupled to a switch node ( 13 ) in a synchronous DC-DC converter ( 10 ). The DC-DC converter includes a high-side switch ( 11 ) and a low-side switch ( 12 ). The sense FET device ( 31 ) senses current conduction in a body diode ( 18 ) of the low-side switch ( 12 ). A current sensing/comparator circuit ( 32 ) coupled to the sense FET ( 31 ) detects changes in current conduction. A delay circuit ( 33 ) and a clock/logic circuit ( 32 ) coupled to the current sensing/comparator circuit ( 32 ) predict and adjust delay time in switching between the high-side switch ( 11 ) and the low-side switch ( 12 ).
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Inventors:
Shee, Sente Kevin
Application Number:
JP2004266373A
Publication Date:
August 18, 2010
Filing Date:
September 14, 2004
Export Citation:
Assignee:
Semiconductor Components Industries Limited Liability Company
International Classes:
H02M3/155; H02M1/00; H02M1/38; H02M3/07; H02M3/158
Domestic Patent References:
| JP8288811A |
Attorney, Agent or Firm:
Masanori Honjo
Yoshiko Honjo
Yoshiko Honjo