Title:
デジタルディスプレイ装置におけるEMIを低減するための方法および装置
Document Type and Number:
Japanese Patent JP4500920
Kind Code:
B2
Abstract:
A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.
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Inventors:
One Vincent
Application Number:
JP2003577437A
Publication Date:
July 14, 2010
Filing Date:
March 12, 2003
Export Citation:
Assignee:
Tamiras Per Pte.Ltd.,LLC
International Classes:
H04J13/00; H04B1/707; H04B15/04
Domestic Patent References:
| JP2000125149A | ||||
| JP3265014A | ||||
| JP9098152A | ||||
| JP9501815A | ||||
| JP4054033A |
Foreign References:
| US5382913 |
Attorney, Agent or Firm:
Meisei International Patent Office