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Title:
集積回路内に電池を形成する方法と装置
Document Type and Number:
Japanese Patent JP4726391
Kind Code:
B2
Abstract:
A method and structure that provides a battery within an integrated circuit for providing voltage to low-current electronic devices that exist within the integrated circuit. The method includes Front-End-Of-Line (FEOL) processing for generating a layer of electronic devices on a semiconductor wafer, followed by Back-End-Of-Line (BEOL) integration for wires connecting the electronic devices together to form completed electrical circuits of the integrated circuit. The BEOL integration includes forming a multilayered structure of wiring levels on the layer of electronic devices. Each wiring level includes conductive metallization (e.g., metal-plated vias, conductive wiring lines, etc.) embedded in insulative material. The battery is formed during BEOL integration within one or more wiring levels, and the conductive metallization conductively couples positive and negative terminals of the battery to the electronic devices. The battery may have several different topologies relative to the structural and geometrical relationships among the battery electrodes and electrolyte. Multiple batteries may be formed within one or more wiring levels, and may be conductively coupled to the electronic devices. The multiple batteries may be connected in series or in parallel.

Inventors:
Ballantine, Earn
Groves, Robert
Lund, Jennifer
Nacos, james
Rice, michael
Stamper, anthony
Application Number:
JP2002558335A
Publication Date:
July 20, 2011
Filing Date:
January 11, 2002
Export Citation:
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Assignee:
INTERNATIONAL BUSINESS MASCHINES CORPORATION
International Classes:
H01L21/768; H01L21/822; H01L23/522; H01L23/58; H01L27/04; H01M4/48; H01M4/58; H01M6/02; H01M6/18; H01M10/052; H01M10/36; H01M6/42; H01M10/0562; H01M10/058; H01M10/42
Domestic Patent References:
JP2000106366A
JP6153412A
JP58125295A
JP5925531A
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City