Title:
単一の命令に応答して演算を複数回実行する方法および装置
Document Type and Number:
Japanese Patent JP3608797
Kind Code:
B2
Abstract:
A method for operating a Reduced Instruction Set Computer (RISC) processor that executes normal RISC instructions and special RISC instructions. The method comprises the step of controlling the RISC processor to perform a single operation, using a single functional unit of the RISC processor, in response to each normal RISC instruction. The method also comprises the step of controlling the RISC processor to perform multiple operations, using multiple functional units of the RISC processor in parallel, in response to each special RISC instruction.
Inventors:
James Earl, Peterson
Pool, Glen Shii
Sritty, Mohamed
Pool, Glen Shii
Sritty, Mohamed
Application Number:
JP53265997A
Publication Date:
January 12, 2005
Filing Date:
March 04, 1997
Export Citation:
Assignee:
Micron Technology Incorporated
International Classes:
G06F9/30; G06F9/32; G06F9/38; (IPC1-7): G06F9/38; G06F9/30
Domestic Patent References:
| JP7152557A | ||||
| JP7244588A | ||||
| JP651984A | ||||
| JP3263127A | ||||
| JP62233839A |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa