Title:
電力節約動作モードをサポートする方法と装置
Document Type and Number:
Japanese Patent JP4191254
Kind Code:
B2
Abstract:
An apparatus for managing power in an electronic device that receives the power from a bus is described. The apparatus comprises a clock enable circuit that disables a clock that generates nominal clock frequencies derived from raw frequencies output by an oscillator upon receiving a first signal. A time-wise independent time reference circuit is coupled to the clock enable circuit. The time-wise independent time reference circuit sends the first signal to the clock enable circuit a first predetermined period of time after receiving a signal to enter into a suspend state.
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Inventors:
David Earl Jackson
Cross, Leonard W
Jacobs, Robert A
Ozta Skin, Ali S
Cross, Leonard W
Jacobs, Robert A
Ozta Skin, Ali S
Application Number:
JP52771198A
Publication Date:
December 03, 2008
Filing Date:
November 18, 1997
Export Citation:
Assignee:
INTEL CORPORATION
International Classes:
G06F1/32; G06F1/04; G06F1/08; G06F13/38
Domestic Patent References:
| JP6104815A | ||||
| JP6289949A | ||||
| JP7093061A | ||||
| JP7200093A | ||||
| JP7271538A | ||||
| JP8221163A | ||||
| JP4094668U |
Attorney, Agent or Firm:
Masaki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa
Hiroro Kurokawa
Masayuki Konno
Osamu Nishiyama
Jiro Suzuki
Shigeki Yamakawa